Such circuits are commonly used with voltage controlled oscillators (VCO) in phase locked loops (PLL). The circuit comprises an interpolator unit which receives two input signals of similar phase and frequency but slightly different in phase from the VCO and outputs the desired clock signal with a phase interpolated between the phase of the first input signal and the second input signal. The design and function of this interpolator is known in the art for example from DE 100 28 603. The interpolator is controlled externally to determine the phase of the clock signal relative to either one of the first input signal or the second input signal. To change the phase of the clock output signal, a phase step has to be executed. This phase step is executed by the interpolator unit shifting the phase of the clock signal closer to the phase of either the first or the second input signal when it receives a phase step command. When the phase step is executed, the following crosspoint between the complementary output signals is shifted, which means that one period of the clock signal is extended in duration. Capacitive coupling through switches within the interpolator can cause an additional shift of the following crosspoint. As a result, the extended period is prolonged further and the following period is shortened by the same amount. This unintended effect will appear as phase jitter in the generated clock signal.